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[VHDL-FPGA-Verilogserial_VHDL

Description: FPGA进行串口通信的程序 VHDL编写的 -FPGA for serial communication procedure prepared by the VHDL
Platform: | Size: 2048 | Author: 饮血病 | Hits:

[Embeded-SCM DevelopEXPT12_12_VGAgame

Description: 基于fpga和sopc的用VHDL语言编写的EDA的PS/2鼠标与VGA控制模块-FPGA and SOPC based on the use of VHDL language EDA s PS/2 mouse and VGA control module
Platform: | Size: 29696 | Author: 多幅撒 | Hits:

[Embeded-SCM DevelopEP1C6_12_3_VGAimg

Description: 基于fpga和sopc的用VHDL语言编写的EDA的VGA彩条信号显示控制器-FPGA and SOPC based on the use of VHDL language EDA color signal of the VGA display controller
Platform: | Size: 21504 | Author: 多幅撒 | Hits:

[Otherfpga_vga_sync_block

Description: altera fpga 基于vhdl,实现vga的同步block.-altera fpga based on vhdl, achieve vga synchronization block.
Platform: | Size: 173056 | Author: qiuxin_88 | Hits:

[OtherNIOS2full

Description: nios ii 完整版教程,学习fpga,实现32位处理器的嵌入式系统-nios ii full version of tutorial, learning fpga, realize 32-bit processors, embedded systems
Platform: | Size: 1745920 | Author: wuchangyu | Hits:

[VHDL-FPGA-Verilogs8_vga

Description: 用FPGA实现的VGA接口程序,采用的语言是VHDL硬件描述语言,大家可以参照下看看采用的器件是Altera EP2c35-Using FPGA to achieve the VGA interface program, the language used is VHDL hardware description language, we can see under the light of the devices used are Altera EP2c35
Platform: | Size: 438272 | Author: 蔡白银1 | Hits:

[Software Engineeringfpga_docu

Description: CPLD/FPGA 入门文档。国内某知名fpga开发商编写的基础教程,共18篇。从使用fpga如何点亮led灯到VGA到8051内核使用方法。如果您是打算学习cpld/fpga,建议先阅读这些文章再选择采购开发板。-CPLD/FPGA entry documents. FPGA developers a well-known domestic basis for the preparation of curricula, a total of 18. From how to use the FPGA to the VGA lit lamp led to the 8051 core to use. If you intend to study cpld/fpga, we suggest that you first read the article and then select the procurement development board.
Platform: | Size: 5509120 | Author: gao | Hits:

[Software EngineeringFPGAVGA20901114

Description: 基于FPGA的VGA图形控制器的实现方法-Based on the VGA graphics controller FPGA Implementation
Platform: | Size: 642048 | Author: mxl | Hits:

[VHDL-FPGA-VerilogEDA

Description: 这里边有EDA设计常用模块的源代码,FFT,DDS PS2_keyboard,VGA等,有学FPGA的就参考一下吧-Here the design of commonly used modules have EDA source code, FFT, DDS PS2_keyboard, VGA and so on, have places on the FPGA reference yourself
Platform: | Size: 208896 | Author: li | Hits:

[VHDL-FPGA-Verilogusb_FPGA

Description: 实现USB接口功能的VHDL和verilog完整源代码-Implementation USB interface functions of the VHDL and Verilog source code integrity
Platform: | Size: 260096 | Author: liang | Hits:

[OtherVHDL_Core_for_1024_Point_Radix_4_FFT_Computation.

Description: This paper shows the development of a 1024-point radix-4 FFT VHDL core for applications in hardware signal processing, targeting low-cost FPGA technologies. The developed core is targeted into a Xilinx庐 Spartan鈩?3 XC3S200 FPGA with the inclusion of a VGA display interface and an external 16-bit data acquisition system for performance evaluation purposes. Several tests were performed in order to verify FFT core functionality, besides the time performance analysis highlights the core advantages over commercially available DSPs and Pentium-based PCs. The core is compared with similar third party IP cores targeting resourceful FPGA technologies. The novelty of this work is to provide a lowcost, resource efficient core for spectrum analysis applications.
Platform: | Size: 456704 | Author: alex | Hits:

[VHDL-FPGA-Verilogfpga

Description:
Platform: | Size: 358400 | Author: 王立新 | Hits:

[Linux-UnixLinux_bc

Description: 对vga接口做了详细的介绍,并且有一 ·三段式Verilog的IDE程序,但只有DMA ·电子密码锁,基于fpga实现,密码正 ·IIR、FIR、FFT各模块程序设计例程, ·基于逻辑工具的以太网开发,基于逻 ·自己写的一个测温元件(ds18b20)的 ·光纤通信中的SDH数据帧解析及提取的 ·VHDL Programming by Example(McGr ·这是CAN总线控制器的IP核,源码是由 ·FPGA设计的SDRAM控制器,有仿真代码 ·xilinx fpga 下的IDE控制器原代码, ·用verilog写的,基于查表法实现的LO ·精通verilog HDL语言编- up:in STD_LOGIC down:in STD_LOGIC run_stop:in STD_LOGIC wai_t: in std_logic_vector(2 downto 0) lift:in std_logic_vector(2 downto 0) ladd: out std_logic_vector(1 downto 0) ) end control
Platform: | Size: 18683904 | Author: liuzhou | Hits:

[Othersource_code

Description: 基于FPGA的vga实现,用于显示一行文字"伟杰电子FPGA开发系统 "-FPGA-based realization of the vga, used to display a line of text " Weijie e-FPGA Development System"
Platform: | Size: 3072 | Author: 陈阳光 | Hits:

[Other Embeded programballgame

Description: 使用FPGA开发的小球挡板游戏 用vga视频接口输出-The development of the use of FPGA baffle ball game with vga output video interface
Platform: | Size: 5120 | Author: 薛睿 | Hits:

[Graph programImageProcessing

Description: 应用不同的用户可选择回旋滤波器的图像处理部件。一套PC应用程序将图像档案下载到一个FPGA可访问的存储器阵列。处理过的图像显示在连接的VGA显示屏上。 -Users can choose to apply a different room of the image processing filter components. A set of PC applications will be image files downloaded to a FPGA can access the memory array. Processed image displayed on the VGA display connection.
Platform: | Size: 15406080 | Author: chenlunhai | Hits:

[VHDL-FPGA-VerilogVGAWorm

Description: VGA game implemented on FPGA
Platform: | Size: 630784 | Author: picasso | Hits:

[VHDL-FPGA-Verilog080637

Description: 基于FPGA的VGA显示控制器的实现 VGA作为一种标准的显示接口得到广泛的应用。本论文依据VGA接口设计原理,采用VHDL语言以及Altera 公司的Cyclone系列FPGA进行VGA显示控制器的设计,最后给出了Ouartus II的仿真结果。-As a standard display interface,VGA has been widely used.According to the designing principle ofVGA interface, Use VttDL and the FPGA ofCompany AJter’s series Cylone to design the VGA display controller.At last,the simulating resuh of Quanus II is given.
Platform: | Size: 140288 | Author: 吕大 | Hits:

[VHDL-FPGA-VerilogVHDL

Description: 再FPGA上經由VGA顯示一半黑一半白的圖示-By the FPGA and then VGA display half black half white icon
Platform: | Size: 1024 | Author: KICK | Hits:

[VHDL-FPGA-Verilogcameralink

Description: 由于目前基于CameraLink接口的各种相机都不能直接显示,因此本文基于Xilinx公司的Spartan 3系列FPGAXC3S1000-6FG456I设计了一套实时显示系统,该系统可以在不通过系统机的情况下,完成对相机CameraLink信号的接收、缓存、读取并显示 系统采用两片SDRAM作为帧缓存,将输入的CameraLink信号转换成帧频为75Hz,分辨率为1 024×768的XGA格式信号,并采用ADV7123JST芯片实现数模转换,将芯片输出的信号送到VGA接口,通过VGA显示器显示出来-As the CameraLink interface is currently based on a variety of cameras can not directly display, this article based on Xilinx' s Spartan 3 series FPGAXC3S1000-6FG456I designed a set of real-time display system, the system can be achieved without machine case through the system to complete the CameraLink cameras signal reception, cache, read and display systems use two SDRAM frame buffer as the input signals into the CameraLink frame rate of 75Hz, a resolution of 1 024 × 768 for XGA format signal, and using ADV7123JST chip digital-analog conversion, the chip output signal to the VGA port, through the VGA display monitor
Platform: | Size: 13312 | Author: lilei | Hits:
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